circuit cim_mvm :
  module cim_rom2 :
    input clock : Clock
    input reset : UInt<1>
    input io_a : UInt<3>
    output io_spo : UInt<8>

    node _T = bits(io_a, 1, 0)
    node mem_0 = pad(UInt<5>("h12"), 8) @[cim_mvm.scala 24:20 cim_mvm.scala 24:20]
    node _GEN_0 = validif(eq(UInt<1>("h0"), _T), mem_0) @[cim_mvm.scala 25:10 cim_mvm.scala 25:10]
    node mem_1 = UInt<8>("h81") @[cim_mvm.scala 24:20 cim_mvm.scala 24:20]
    node _GEN_1 = mux(eq(UInt<1>("h1"), _T), mem_1, _GEN_0) @[cim_mvm.scala 25:10 cim_mvm.scala 25:10]
    node mem_2 = UInt<8>("hd1") @[cim_mvm.scala 24:20 cim_mvm.scala 24:20]
    node _GEN_2 = mux(eq(UInt<2>("h2"), _T), mem_2, _GEN_1) @[cim_mvm.scala 25:10 cim_mvm.scala 25:10]
    node mem_3 = UInt<8>("hff") @[cim_mvm.scala 24:20 cim_mvm.scala 24:20]
    node _GEN_3 = mux(eq(UInt<2>("h3"), _T), mem_3, _GEN_2) @[cim_mvm.scala 25:10 cim_mvm.scala 25:10]
    node _mem_T = _GEN_3 @[cim_mvm.scala 25:10]
    io_spo <= _mem_T @[cim_mvm.scala 25:10]

  module cim_mvm :
    input clock : Clock
    input reset : UInt<1>
    input io_start : UInt<1>
    output io_mvm_done : UInt<1>
    input io_rcil_row_index : UInt<3>
    input io_rcil_col_index : UInt<2>
    input io_rcil_row_length : UInt<3>
    input io_rcil_col_length : UInt<2>
    input io_push_buf : UInt<8>
    output io_save_buf : UInt<32>

    inst rom of cim_rom2 @[cim_mvm.scala 61:19]
    reg state : UInt<2>, clock with :
      reset => (UInt<1>("h0"), state) @[cim_mvm.scala 43:22]
    node _T = eq(UInt<2>("h0"), state) @[Conditional.scala 37:30]
    node _T_1 = mux(io_start, UInt<2>("h1"), UInt<2>("h0")) @[cim_mvm.scala 45:29]
    node _T_2 = eq(UInt<2>("h1"), state) @[Conditional.scala 37:30]
    node _T_3 = eq(UInt<2>("h2"), state) @[Conditional.scala 37:30]
    node _T_4 = mux(io_mvm_done, UInt<2>("h0"), UInt<2>("h2")) @[cim_mvm.scala 47:29]
    node _GEN_0 = mux(_T_3, _T_4, state) @[Conditional.scala 39:67 cim_mvm.scala 47:23 cim_mvm.scala 43:22]
    node _GEN_1 = mux(_T_2, UInt<2>("h2"), _GEN_0) @[Conditional.scala 39:67 cim_mvm.scala 46:23]
    node _GEN_2 = mux(_T, _T_1, _GEN_1) @[Conditional.scala 40:58 cim_mvm.scala 45:23]
    node _WIRE = io_push_buf
    node _T_5 = bits(_WIRE, 1, 0) @[cim_mvm.scala 50:39]
    node _T_6 = bits(_WIRE, 3, 2) @[cim_mvm.scala 50:39]
    node _T_7 = bits(_WIRE, 5, 4) @[cim_mvm.scala 50:39]
    node _T_8 = bits(_WIRE, 7, 6) @[cim_mvm.scala 50:39]
    reg output_buf_0 : SInt<16>, clock with :
      reset => (UInt<1>("h0"), output_buf_0) @[cim_mvm.scala 51:27]
    reg output_buf_1 : SInt<16>, clock with :
      reset => (UInt<1>("h0"), output_buf_1) @[cim_mvm.scala 51:27]
    reg addr : UInt<3>, clock with :
      reset => (UInt<1>("h0"), addr) @[cim_mvm.scala 52:21]
    node _T_9 = eq(state, UInt<2>("h1")) @[cim_mvm.scala 53:14]
    node _T_10 = eq(state, UInt<2>("h2")) @[cim_mvm.scala 55:19]
    node _T_11 = add(addr, UInt<1>("h1")) @[cim_mvm.scala 56:18]
    node _T_12 = tail(_T_11, 1) @[cim_mvm.scala 56:18]
    node _GEN_3 = mux(_T_10, _T_12, UInt<1>("h0")) @[cim_mvm.scala 55:26 cim_mvm.scala 56:10 cim_mvm.scala 58:10]
    node _GEN_4 = mux(_T_9, io_rcil_row_index, _GEN_3) @[cim_mvm.scala 53:22 cim_mvm.scala 54:10]
    node _WIRE_2 = rom.io_spo
    node _T_13 = bits(_WIRE_2, 3, 0) @[cim_mvm.scala 63:38]
    node _T_14 = asSInt(_T_13) @[cim_mvm.scala 63:38]
    node _T_15 = bits(_WIRE_2, 7, 4) @[cim_mvm.scala 63:38]
    node _T_16 = asSInt(_T_15) @[cim_mvm.scala 63:38]
    node _T_17 = geq(UInt<1>("h0"), io_rcil_col_index) @[cim_mvm.scala 67:27]
    node _T_18 = add(io_rcil_col_index, io_rcil_col_length) @[cim_mvm.scala 67:74]
    node _T_19 = tail(_T_18, 1) @[cim_mvm.scala 67:74]
    node _T_20 = lt(UInt<1>("h0"), _T_19) @[cim_mvm.scala 67:54]
    node _T_21 = and(_T_17, _T_20) @[cim_mvm.scala 67:47]
    node _T_22 = eq(state, UInt<2>("h1")) @[cim_mvm.scala 69:16]
    node _T_23 = eq(state, UInt<2>("h2")) @[cim_mvm.scala 71:21]
    node _T_24 = bits(addr, 1, 0)
    node input_buf_0 = _T_5 @[cim_mvm.scala 50:39 cim_mvm.scala 50:39]
    node _GEN_5 = validif(eq(UInt<1>("h0"), _T_24), input_buf_0) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node input_buf_1 = _T_6 @[cim_mvm.scala 50:39 cim_mvm.scala 50:39]
    node _GEN_6 = mux(eq(UInt<1>("h1"), _T_24), input_buf_1, _GEN_5) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node input_buf_2 = _T_7 @[cim_mvm.scala 50:39 cim_mvm.scala 50:39]
    node _GEN_7 = mux(eq(UInt<2>("h2"), _T_24), input_buf_2, _GEN_6) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node input_buf_3 = _T_8 @[cim_mvm.scala 50:39 cim_mvm.scala 50:39]
    node _GEN_8 = mux(eq(UInt<2>("h3"), _T_24), input_buf_3, _GEN_7) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node _input_buf_T_24 = _GEN_8 @[cim_mvm.scala 73:31]
    node _T_25 = bits(_input_buf_T_24, 1, 1) @[cim_mvm.scala 73:31]
    node _T_26 = bits(_T_25, 0, 0) @[cim_mvm.scala 73:41]
    node rom_out_0 = _T_14 @[cim_mvm.scala 63:38 cim_mvm.scala 63:38]
    node add_num_0 = pad(rom_out_0, 16) @[cim_mvm.scala 65:23 cim_mvm.scala 68:16]
    node _T_27 = sub(asSInt(UInt<1>("h0")), add_num_0) @[cim_mvm.scala 73:44]
    node _T_28 = tail(_T_27, 1) @[cim_mvm.scala 73:44]
    node _T_29 = asSInt(_T_28) @[cim_mvm.scala 73:44]
    node _T_30 = bits(addr, 1, 0)
    node _GEN_9 = validif(eq(UInt<1>("h0"), _T_30), input_buf_0) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _GEN_10 = mux(eq(UInt<1>("h1"), _T_30), input_buf_1, _GEN_9) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _GEN_11 = mux(eq(UInt<2>("h2"), _T_30), input_buf_2, _GEN_10) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _GEN_12 = mux(eq(UInt<2>("h3"), _T_30), input_buf_3, _GEN_11) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _input_buf_T_30 = _GEN_12 @[cim_mvm.scala 74:31]
    node _T_31 = bits(_input_buf_T_30, 0, 0) @[cim_mvm.scala 74:31]
    node _T_32 = bits(_T_31, 0, 0) @[cim_mvm.scala 74:41]
    node _T_33 = mux(_T_32, add_num_0, asSInt(UInt<1>("h0"))) @[cim_mvm.scala 74:15]
    node _T_34 = mux(_T_26, _T_29, _T_33) @[cim_mvm.scala 73:15]
    node _T_35 = add(output_buf_0, _T_34) @[cim_mvm.scala 72:55]
    node _T_36 = tail(_T_35, 1) @[cim_mvm.scala 72:55]
    node _T_37 = asSInt(_T_36) @[cim_mvm.scala 72:55]
    node output_en_0 = _T_21 @[cim_mvm.scala 64:23 cim_mvm.scala 67:18]
    node _T_38 = mux(output_en_0, _T_37, asSInt(UInt<1>("h0"))) @[cim_mvm.scala 72:28]
    node _T_39 = eq(state, UInt<2>("h0")) @[cim_mvm.scala 76:21]
    node _GEN_13 = mux(_T_39, output_buf_0, output_buf_0) @[cim_mvm.scala 76:29 cim_mvm.scala 77:21 cim_mvm.scala 51:27]
    node _GEN_14 = mux(_T_23, _T_38, _GEN_13) @[cim_mvm.scala 71:28 cim_mvm.scala 72:22]
    node _GEN_15 = mux(_T_22, asSInt(UInt<1>("h0")), _GEN_14) @[cim_mvm.scala 69:24 cim_mvm.scala 70:21]
    node _T_40 = geq(UInt<1>("h1"), io_rcil_col_index) @[cim_mvm.scala 67:27]
    node _T_41 = add(io_rcil_col_index, io_rcil_col_length) @[cim_mvm.scala 67:74]
    node _T_42 = tail(_T_41, 1) @[cim_mvm.scala 67:74]
    node _T_43 = lt(UInt<1>("h1"), _T_42) @[cim_mvm.scala 67:54]
    node _T_44 = and(_T_40, _T_43) @[cim_mvm.scala 67:47]
    node _T_45 = eq(state, UInt<2>("h1")) @[cim_mvm.scala 69:16]
    node _T_46 = eq(state, UInt<2>("h2")) @[cim_mvm.scala 71:21]
    node _T_47 = bits(addr, 1, 0)
    node _GEN_16 = validif(eq(UInt<1>("h0"), _T_47), input_buf_0) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node _GEN_17 = mux(eq(UInt<1>("h1"), _T_47), input_buf_1, _GEN_16) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node _GEN_18 = mux(eq(UInt<2>("h2"), _T_47), input_buf_2, _GEN_17) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node _GEN_19 = mux(eq(UInt<2>("h3"), _T_47), input_buf_3, _GEN_18) @[cim_mvm.scala 73:31 cim_mvm.scala 73:31]
    node _input_buf_T_47 = _GEN_19 @[cim_mvm.scala 73:31]
    node _T_48 = bits(_input_buf_T_47, 1, 1) @[cim_mvm.scala 73:31]
    node _T_49 = bits(_T_48, 0, 0) @[cim_mvm.scala 73:41]
    node rom_out_1 = _T_16 @[cim_mvm.scala 63:38 cim_mvm.scala 63:38]
    node add_num_1 = pad(rom_out_1, 16) @[cim_mvm.scala 65:23 cim_mvm.scala 68:16]
    node _T_50 = sub(asSInt(UInt<1>("h0")), add_num_1) @[cim_mvm.scala 73:44]
    node _T_51 = tail(_T_50, 1) @[cim_mvm.scala 73:44]
    node _T_52 = asSInt(_T_51) @[cim_mvm.scala 73:44]
    node _T_53 = bits(addr, 1, 0)
    node _GEN_20 = validif(eq(UInt<1>("h0"), _T_53), input_buf_0) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _GEN_21 = mux(eq(UInt<1>("h1"), _T_53), input_buf_1, _GEN_20) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _GEN_22 = mux(eq(UInt<2>("h2"), _T_53), input_buf_2, _GEN_21) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _GEN_23 = mux(eq(UInt<2>("h3"), _T_53), input_buf_3, _GEN_22) @[cim_mvm.scala 74:31 cim_mvm.scala 74:31]
    node _input_buf_T_53 = _GEN_23 @[cim_mvm.scala 74:31]
    node _T_54 = bits(_input_buf_T_53, 0, 0) @[cim_mvm.scala 74:31]
    node _T_55 = bits(_T_54, 0, 0) @[cim_mvm.scala 74:41]
    node _T_56 = mux(_T_55, add_num_1, asSInt(UInt<1>("h0"))) @[cim_mvm.scala 74:15]
    node _T_57 = mux(_T_49, _T_52, _T_56) @[cim_mvm.scala 73:15]
    node _T_58 = add(output_buf_1, _T_57) @[cim_mvm.scala 72:55]
    node _T_59 = tail(_T_58, 1) @[cim_mvm.scala 72:55]
    node _T_60 = asSInt(_T_59) @[cim_mvm.scala 72:55]
    node output_en_1 = _T_44 @[cim_mvm.scala 64:23 cim_mvm.scala 67:18]
    node _T_61 = mux(output_en_1, _T_60, asSInt(UInt<1>("h0"))) @[cim_mvm.scala 72:28]
    node _T_62 = eq(state, UInt<2>("h0")) @[cim_mvm.scala 76:21]
    node _GEN_24 = mux(_T_62, output_buf_1, output_buf_1) @[cim_mvm.scala 76:29 cim_mvm.scala 77:21 cim_mvm.scala 51:27]
    node _GEN_25 = mux(_T_46, _T_61, _GEN_24) @[cim_mvm.scala 71:28 cim_mvm.scala 72:22]
    node _GEN_26 = mux(_T_45, asSInt(UInt<1>("h0")), _GEN_25) @[cim_mvm.scala 69:24 cim_mvm.scala 70:21]
    node lo = asUInt(output_buf_0) @[cim_mvm.scala 80:35]
    node hi = asUInt(output_buf_1) @[cim_mvm.scala 80:35]
    node _T_63 = cat(hi, lo) @[cim_mvm.scala 80:35]
    node _T_64 = add(io_rcil_row_index, io_rcil_row_length) @[cim_mvm.scala 81:46]
    node _T_65 = tail(_T_64, 1) @[cim_mvm.scala 81:46]
    node _T_66 = sub(_T_65, UInt<1>("h1")) @[cim_mvm.scala 81:66]
    node _T_67 = tail(_T_66, 1) @[cim_mvm.scala 81:66]
    node _T_68 = eq(addr, _T_67) @[cim_mvm.scala 81:24]
    node _WIRE_1_0 = asSInt(UInt<16>("h0")) @[cim_mvm.scala 51:35 cim_mvm.scala 51:35]
    node _WIRE_1_1 = asSInt(UInt<16>("h0")) @[cim_mvm.scala 51:35 cim_mvm.scala 51:35]
    io_mvm_done <= _T_68 @[cim_mvm.scala 81:15]
    io_save_buf <= _T_63 @[cim_mvm.scala 80:15]
    state <= mux(reset, UInt<2>("h0"), _GEN_2) @[cim_mvm.scala 43:22 cim_mvm.scala 43:22]
    output_buf_0 <= mux(reset, _WIRE_1_0, _GEN_15) @[cim_mvm.scala 51:27 cim_mvm.scala 51:27]
    output_buf_1 <= mux(reset, _WIRE_1_1, _GEN_26) @[cim_mvm.scala 51:27 cim_mvm.scala 51:27]
    addr <= mux(reset, UInt<1>("h0"), _GEN_4) @[cim_mvm.scala 52:21 cim_mvm.scala 52:21]
    rom.clock <= clock
    rom.reset <= reset
    rom.io_a <= addr @[cim_mvm.scala 62:12]